1. Field of the Invention
The present invention relates to a semiconductor memory device used for cache memory. The semiconductor memory device of the present invention is used as a multi-bit length cache memory built in a system LSI for broadband communication, for example.
2. Description of the Related Art
Recently, with high speed and high function of system LSI, data exchange must be made between main memory and central processing unit (CPU) at high speed. Thus, a cache memory interposed between both elements described above is very important. In particular, a large amount of data must be processed in the system LSI at high speed in order to meet the needs of the broadband time. For this reason, a multi-bit length cache memory is required.
In general, Dynamic Random Access Memory (DRAM) is used as the external main memory in the system LSI mounted with CPU. The DRAM has a large memory capacity, but long access time is taken to make data exchange. On the contrary, the cache memory comprises Static Random Access Memory (SRAM). The SRAM has a small memory capacity, but it can make data access at high speed.
In order to achieve the high-speed operation of the system LSI having a built-in CPU, the number of access times to the DRAM spending much time taken to access need to be reduced. For this reason, a large amount of data such as 256 bytes or 512 bytes is previously stored in the cache memory. The bit length of a data bus interposed between cache memory and CPU is, for example, 32 bits or 64 bits, although depending on the system. The data size transferred at one time between main memory and cache memory is several times as much as the same between cache memory and CPU.
In general, the cache memory is composed of a data memory circuit including a SRAM cell, and a tag circuit including a Content Addressable Memory (hereinafter, referred to as CAM). More specifically, the SRAM cell temporarily stores cache data, which is data copy of part of the main memory. The CAM stores address corresponding to data stored in the data memory circuit, that is, part of address supplied from a fetch counter provided in the CPU.
If necessary data is stored in the cache memory, that is, if the data hits on the cache memory, the input address is compared with the address held in the tag circuit. Thereafter, data of the data memory circuit corresponding to the matched entry is read. Basically, the tag circuit and the data memory circuit make one-to-one correspondence, and with the development of broadband, the data size handled by the cache memory is becoming larger.
In view of the circumstances described above, the following cache memory has been proposed in order to soften the limitation of bus width in the system LSI, and to reduce the LSI chip area. In the cache memory, the row direction length of the data memory circuit, that is, bit length is divided into several parts so that data can be stored in several rows. Write data is written to these several rows at divided several cycles.
FIG. 1 shows a conventional example of the cell array pattern layout in a cache memory, which is configured in a manner that one unit data is stored in divided two rows by a data memory circuit. The cache memory includes a data memory circuit 10 and a tag circuit 80.
The data memory circuit 10 stores data input from the main memory. The tag circuit 80 is provided with several CAM cells having a function of comparing address. The tag circuit 80 has a function of storing write address of the main memory corresponding to data stored in the data memory circuit 10 and compare address input from a CPU, and making comparison between both addresses.
When one unit data is stored divided two rows by the data memory circuit 10, data write to the data memory circuit 10 requires two entries. It is determined by index address which of two entries should be selected. On the contrary, the write of write address to the tag circuit 80 requires only one entry.
In the conventional cache memory, the array configuration of the tag circuit 80 is determined depending on the bit length of write data. When a large amount of data for broadband communication is handled, the data size becomes very large. For this reason, the physical length of the word line direction of the tag circuit 80 becomes extremely long. This is a factor of hindering high-speed operation.
The configuration of memory cell differs from the tag circuit 80 and the data memory circuit 10. The data memory circuit 10 requires the number of many entries. For this reason, clearances 90 generated in the cell array of the tag circuit 80 increase as seen from FIG. 1; as a result, wasteful areas are generated. Thus, the area of an LSI chip integrated with the foregoing cache memory also increases.
In addition, with high speed and high function of the cache memory, the configuration of the memory cell becomes complicate in the data memory circuit 10. If the pursuit of the optimal aspect ratio is made, the physical layout height of the cache memory increases. In this case, the data memory circuit 10 is higher than the tag circuit 80 in the physical layout height. For this reason, clearance is generated in the pattern layout of the cache memory; as a result, wasteful area is generated in the LSI chip area.
U.S. patent Ser. No. 5,752,260 discloses the cache memory in which two-series CAM cells are provided, and the CAM cell compares three addresses, that is, two virtual addresses and one real address. In this case, a plurality of CAM cells is divided in the word line direction, and a match line is led every divided CAM cell. A selector selects one from several match lines. The output of the selector is latched, and thereafter, used as a signal for driving the CAM and the word line of the data memory circuit. Thus, the next data is set up during data read. Data equivalent to two blocks is read from a single cache line.
As seen from the foregoing description, the conventional cache memory has the following problems. That is, the data size becomes large, and thereby, the physical length of the word line direction becomes extremely long. As a result, the high-speed operation is hindered. In addition, clearance increases in the cell array of the tag circuit, and wasteful areas are generated; as a result, the LSI chip area increases. Therefore, it is desired to solve the conventional problems described above.